Chip fabrication roadblock solved?

Today on http://www.embedded.com I read this article about the potential solution to a chip fabrication problem inherent in the physics of microelectronics. Gate leakage is current that is pulled between the gate and the channel in a transistor. As chips get smaller and smaller, the distance and amount of insulator between the gate and the channel is decreased and current drain between the gate and channel becomes more of a problem.

" "The biggest problem with going below 65 nanometers is gate leakage, and Mears appears to have a solution to it," said Morry Marshall, vice president of stategic technology at Semico Research Corp. (Phoenix)."

It seems that a small semiconductor startup company called Mears Technologies claims they have further hindered gate leakage. The process sounds doable since not only do they decrease the leakage but increase the channel mobility. Increasing the channel mobility decreases the Vgs and Vgd thus inherently decreasing leakage.

Since the article says the process can be applied to current fabrication techniques it will be quite interesting to see if it works and if it is adopted by the semiconductor industry.

Understanding gate leakage and other semiconductor properties is a core focus in VLSI courses found in higher university courses.

Last semi roadblock cleared? Article
http://www.embedded.com/showArticle.jhtml;jsessionid=24PYGT4UFJBVEQSNDLPSKHSCJUNN2JVN?articleID=196604395

Efficient Techniques for Gate Leakage Estimation:
http://www.eecs.umich.edu/~brown/Publications/ISLPED-Rao03.pdf

“CMOS VLSI Design” by David Harris – Textbook site (VERY good resource)
http://www.cmosvlsi.com/

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