Junior Lab project 1 - version 2 VHDL!

So a little update to the Traffic light controller project from last year.

This year (my senior year at Clarkson) I am the TA for the new Juniors in Junior Lab. Thus I get to have a say in what projects they do and I get to grade them when their projects don't work...er... are done.

For lab 4 this year we designed a project using the Xilinx CoolRunner II development board I made mention of in the tech log. Attached to this board is the DIO1 board from digilent ( http://www.digilentinc.com/ ). The connections between the CPLD and the DIO1 and how to control the faetures of the DIO1 are confusing. So, to minimise the confusion I took lab 1 and implemented it on the CPLD as an example of how to interface with the DIO1.

I decided to post the VHDL for this for anyone to download. It's cool, three of the four seven-segment displays are used to count down the different times and the 8 LED bank is nicely R,Y,G,R,Y,G,R,R. Thus the upper 3 LEDs are the RYG for the EW, the next are for the NS and the final two red LEDs are for the pedestrian (we just pretend the bottom one is green).

The project was perfect for the chip, using only 26% of the minterms.

If you know VHDL or have these boards, check it out!

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